1. Field of the Invention
This invention relates generally to processors, and more specifically, to a system and method for allowing a two word "jump" instruction to be executed in the same number of cycles as a single word "jump" instruction, thereby allowing a processor system to increase addressable memory space without reducing performance.
2. Background of the Invention
Presently, in some processor systems, all instructions are single word instructions. This means that a single word is used to inform the processor of each specific operation to be performed. A problem with single word instructions is that they limit the amount of addressable memory space since single word instructions only have a limited number of address bits.
In order to increase the addressable memory space, some processor systems implement a paging scheme in the program memory. In a paging scheme, the program memory is divided into a plurality of pages. A bit or bits in a data file location will indicate which page in the program memory is currently being accessed. The problem with paging schemes is that in order to access data in a different page (i.e., a page different from the currently selected page) the bit or bits in the data file location need to be changed. This creates a lot of problems for the end user especially if a programmer did not properly change the data file bit(s) when required.
Therefore, a need exists to provide a system for increasing the addressable memory space to be used by a processor. The system must increase the addressable memory space to be used by the processor without reducing the overall performance of the processor. The system must increase the addressable memory space without using a paging scheme and without reducing the overall performance of the processor. The system must increase the addressable memory space without reducing the overall performance of the processor by allowing two word jump instructions to be executed in the same number of cycles as a single jump instruction.